In semiconductor processing, the process of photolithography is utilized to pattern the dimensions of various portions of devices and circuits. In the process of photolithography, a form of radiant energy, for example ultraviolet light, is passed through a reticle or mask and onto a target such as a semiconductor wafer. The reticle contains opaque and transparent regions formed in a predetermined pattern. The ultraviolet light exposes the reticle pattern on a layer of photoresist previously formed on the target. The photoresist is then developed for removing either the exposed portions of photoresist for a positive resist or the unexposed portions of photoresist for a negative resist. The patterned photoresist can then be used during a subsequent fabrication process such as etching, deposition or implantation.
Photoresist is conventionally applied to targets by means of a spinning process. In accordance with this process, the target or structure to which the photoresist is to be applied is secured to a chuck. A quantity of photoresist is then deposited in the center of the target which is either already being spun or is subsequently rotated. Centrifugal forces which are created by spinning spread the photoresist across the target with excess photoresist being thrown off the edges of the target. This spinning process results in the application of a layer of photoresist to the target. Other techniques have also been employed to apply a layer of photoresist onto a target. For example, photoresist has been extruded into a continuous sheet form while the target is moved under the extrusion nozzle so as to apply a wide, thick layer of photoresist onto the target. Chemical vapor deposition in which the photoresist is deposited in the presence of a plasma onto the surface of a target has also been used for application of photoresist layers. In addition, resist sputtering techniques have been employed. In general, each of these methods is not entirely suitable for forming a layer of resist on silicon substrates having uneven or non-planar topographies.
In the semiconductor industry, silicon structures are constantly being developed which are non-planar. For example, interconnects for establishing temporary electrical connection to contact locations on unpackaged semiconductor dice have been developed for testing dice to ensure that the reliability thereof is equivalent to packaged dice. These interconnects can include a substrate formed of a material such as silicon. Raised projections can be formed integrally with the substrate as contact members for contacting the contact locations on the dice. These projections are formed in a pattern that matches the size and spacing of the contact locations on the dice. The height of each projection as measured from the top of the substrate to the tip of the projection can vary from a few angstroms to about 100 .mu.m. In a subsequent photopatterning process it is difficult to apply photoresist to the raised projections because the photoresist falls off the raised topography and pools along the lower portions of the substrate.
Another example of a non-planar topography that is difficult to uniformly coat with photoresist occurs in the manufacture of DRAMs. In some cases metallization interconnect layers must be formed on wafers having an extreme topography. An uneven or non-uniform topography can be caused by the stacking of various semiconductor devices beneath the interconnect layers. By way of example commonly assigned, U.S. Pat. No. 5,354,705 to Mathews et al., discloses a method for forming semiconductor container structures having an uneven topography. Coating resist on these types of topographies using conventional techniques leads to a non-uniform resist thickness. The non-uniform resist exposes unevenly, which can result in the loss of some critical dimensions for the circuits ultimately formed. To overcome this problem planarization of uneven surface topographies is sometimes employed using etchback or chemical mechanical planarization (CMP) processes. However, these planarization processes are expensive and time consuming and can introduce other variables into a manufacturing process.
Other silicon structures such as baseplates used to construct field emitter sites for flat panel displays can also have raised topographies and projecting structures of varying height. When it is necessary to apply photoresist to these raised, non-planar topographies, the conventional application methods as described above provide poor results. In particular the photoresist can not be applied with a uniform thickness over the non-planar area and does not adequately cover the tips and sidewalls of various projecting structures or plateaus.